Electronic systems and circuits have made a significant contribution towards the advancement of modern society and are utilized in a number of applications to achieve advantageous results. Numerous electronic technologies such as digital computers, calculators, audio devices, video equipment, and telephone systems facilitate increased productivity and cost reductions in analyzing and communicating data, ideas and trends in most areas of business, science, education and entertainment. These results are often provided by systems that perform complicated computational operations, including operations associated with coding and cryptography techniques utilizing Galois fields. Many coding and cryptography applications require the operations to be completed quickly and slow results can have adverse impacts on performance. However, traditional Galois field computation approaches often involve a relatively significant amount of resources and/or a large number of computation iterations that require a relatively long time to complete.
As various information processing systems advance and proliferate, reliable and efficient information communication and/or storage systems are becoming more important and often critical. Emerging large-scale and/or fast systems (e.g., storage devices, data networks, etc.) often require effective and dependable handling of vast amounts of information. Traditional systems often utilize Galois field multiplication and division to facilitate accurate and dependable exchange, processing and retention of information in a variety of applications. For example, Galois field computations are often used to ensure information is secure and/or an accurately reproduced.
Reliably “reproducing” data without errors (e.g., introduced by a signal “corrupted” during communication) is one typical major concern in both the communication and storage of information. Error detection and correction schemes typically involve encoding/decoding information “messages”. For example, a message is typically divided into blocks of k information bits each with a total of 2k different possible messages. An encoder transforms each message into an n-tuple vector of discrete symbols called a code word or code vector. Code words and/or encrypted messages are often encoded and decoded utilizing Galois field manipulation. For example, codewords of cyclic codes are conveniently represented as Galois field polynomials that are encoded and decoded using multiplication and division of the Galois field representation.
Galois field multiplication and division can also be utilized in cryptography operations by encoding messages to permit secure communication over an otherwise insecure communication channel. Cryptography systems usually involve manipulations of a message in accordance with a “key” and encryption/decryption rules. Traditionally, keys are utilized in both symmetric cryptographic system (e.g., based on a secret “key”) and asymmetric cryptographic systems (e.g., based upon a public-private key pair). The underlying operations involved in these cryptography systems often involve Galois field multiplication and division of the messages and keys to encrypt/decrypt cyphertext.
Traditional Galois field GF(2m) multiplication and division approaches often utilize single bitwise serial or parallel operations. Traditional parallel GF(2m) multipliers typically generate n partial products and n feedback terms each n bits wide. Then an exclusive OR (XOR) of the n partial products and n feedback terms is performed to get a single final product. Bit parallel multipliers generally provide results in one clock cycle (output bits are calculated in one clock cycle) and involve significant hardware (e.g., silicon area) requirements. The significant hardware requirements of bit parallel multipliers often make them impractical for a number of large degree applications (e.g., a 2128 multiplier for authentication in CPS GCM mode). Serial bit multipliers typically require less hardware and are usually well suited for normal basis representation allowing efficient expontentiation.
While serial bit multipliers typically require less hardware, serial bit multipliers usually require multiple clock cycles to provide a final output. In conventional GF(2m) serial approaches, a single bit is usually entered for each iteration (e.g., one output bit is calculated per clock cycle). For example, in a typical traditional serial multiplier approach one bit of a multiplier generates one partial product. Since the inputs (e.g., multiplier, quotient, etc) usually have a rather large number of bits, conventional approaches produce a relatively large number of partial products that require a significant number of XOR iterations, which can take a relatively significant amount of time to complete (e.g., due to large iteration delays).